cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: MyScopeMain                         Date: 11-30-2008, 12:20PM
Device Used: XC9572-15-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
32 /72  ( 44%) 78  /360  ( 22%) 94 /144 ( 65%)   27 /72  ( 37%) 27 /34  ( 79%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           3/18       18/36       18          10/90       3/ 9
FB2           6/18       15/36       15          18/90       6/ 9
FB3          14/18       32/36       32          24/90       4/ 8
FB4           9/18       29/36       29          26/90       8/ 8*
             -----       -----                   -----       -----     
             32/72       94/144                  78/360     21/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'M50' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :    26      28
Output        :    5           5    |  GCK/IO           :     1       3
Bidirectional :   16          16    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 32 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 21 Outputs **

Signal                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                            Pts   Inps          No.  Type    Use     Mode Rate State
ADR<7>                          3     9     FB1_2   1    I/O     I/O     STD  FAST RESET
ADR<14>                         3     16    FB1_5   2    I/O     I/O     STD  FAST RESET
STOP                            4     18    FB1_15  8    I/O     O       STD  FAST SET
ADR<9>                          3     11    FB2_2   35   I/O     I/O     STD  FAST RESET
ADR<5>                          3     7     FB2_5   36   I/O     I/O     STD  FAST RESET
ADR<8>                          3     10    FB2_6   37   I/O     I/O     STD  FAST RESET
ADR<6>                          3     8     FB2_8   38   I/O     I/O     STD  FAST RESET
ADR<13>                         3     15    FB2_15  43   I/O     I/O     STD  FAST RESET
ADR<12>                         3     14    FB2_17  44   I/O     I/O     STD  FAST RESET
ADR<15>                         3     17    FB3_9   14   I/O     I/O     STD  FAST RESET
AD_CLK                          4     6     FB3_11  18   I/O     O       STD  FAST 
CS                              0     0     FB3_15  20   I/O     O       STD  FAST 
WE                              4     8     FB3_17  22   I/O     O       STD  FAST 
OE                              5     9     FB4_2   24   I/O     O       STD  FAST 
ADR<0>                          2     2     FB4_5   25   I/O     I/O     STD  FAST RESET
ADR<1>                          3     3     FB4_8   26   I/O     I/O     STD  FAST RESET
ADR<10>                         3     12    FB4_9   27   I/O     I/O     STD  FAST RESET
ADR<2>                          3     4     FB4_11  28   I/O     I/O     STD  FAST RESET
ADR<3>                          3     5     FB4_14  29   I/O     I/O     STD  FAST RESET
ADR<11>                         3     13    FB4_15  33   I/O     I/O     STD  FAST RESET
ADR<4>                          3     6     FB4_17  34   I/O     I/O     STD  FAST RESET

** 11 Buried Nodes **

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
XLXI_67/Q<8>                    1     8     FB3_5   STD  RESET
XLXI_67/Q<6>                    1     6     FB3_6   STD  RESET
XLXI_67/Q<5>                    1     5     FB3_7   STD  RESET
XLXI_67/Q<3>                    1     3     FB3_8   STD  RESET
XLXI_67/Q<2>                    1     2     FB3_10  STD  RESET
XLXI_67/Q<1>                    1     1     FB3_12  STD  RESET
XLXI_67/Q<0>                    0     0     FB3_13  STD  RESET
Teiler<7>                       1     7     FB3_14  STD  RESET
Teiler<4>                       1     4     FB3_16  STD  RESET
STOP_OBUF/STOP_OBUF_CLKF__$INT  5     9     FB3_18  STD  
Teiler<9>                       1     9     FB4_18  STD  RESET

** 6 Inputs **

Signal                          Loc     Pin  Pin     Pin     
Name                                    No.  Type    Use     
RESET                           FB1_6   3    I/O     I
RUN                             FB1_8   4    I/O     I
M50                             FB1_9   5    GCK/I/O GCK/I
CLK                             FB1_17  9    I/O     I
DIV0                            FB3_2   11   I/O     I
DIV1                            FB3_5   12   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
ADR<7>                3       0     0   2     FB1_2   1     I/O     I/O
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
ADR<14>               3       0     0   2     FB1_5   2     I/O     I/O
(unused)              0       0     0   5     FB1_6   3     I/O     I
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   4     I/O     I
(unused)              0       0     0   5     FB1_9   5     GCK/I/O GCK/I
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  6     GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  7     GCK/I/O 
STOP                  4       0     0   1     FB1_15  8     I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  9     I/O     I
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: ADR<0>.PIN         7: ADR<1>.PIN        13: ADR<8>.PIN 
  2: ADR<10>.PIN        8: ADR<2>.PIN        14: ADR<9>.PIN 
  3: ADR<11>.PIN        9: ADR<3>.PIN        15: ADR_14_OBUF.LFBK 
  4: ADR<12>.PIN       10: ADR<4>.PIN        16: ADR_7_OBUF.LFBK 
  5: ADR<13>.PIN       11: ADR<5>.PIN        17: RESET 
  6: ADR<15>.PIN       12: ADR<6>.PIN        18: STOP_OBUF/STOP_OBUF_CLKF__$INT 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ADR<7>               X.....XXXXXX....XX...................... 9       9
ADR<14>              XXXXX.XXXXXXXX.XXX...................... 16      16
STOP                 XXXXXXXXXXXXXXXXXX...................... 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               15/21
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
ADR<9>                3       0     0   2     FB2_2   35    I/O     I/O
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
ADR<5>                3       0     0   2     FB2_5   36    I/O     I/O
ADR<8>                3       0     0   2     FB2_6   37    I/O     I/O
(unused)              0       0     0   5     FB2_7         (b)     
ADR<6>                3       0     0   2     FB2_8   38    I/O     I/O
(unused)              0       0     0   5     FB2_9   39    GSR/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O 
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  42    GTS/I/O 
ADR<13>               3       0     0   2     FB2_15  43    I/O     I/O
(unused)              0       0     0   5     FB2_16        (b)     
ADR<12>               3       0     0   2     FB2_17  44    I/O     I/O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: ADR<0>.PIN         6: ADR<3>.PIN        11: ADR_6_OBUF.LFBK 
  2: ADR<10>.PIN        7: ADR<4>.PIN        12: ADR_8_OBUF.LFBK 
  3: ADR<11>.PIN        8: ADR<7>.PIN        13: ADR_9_OBUF.LFBK 
  4: ADR<1>.PIN         9: ADR_12_OBUF.LFBK  14: RESET 
  5: ADR<2>.PIN        10: ADR_5_OBUF.LFBK   15: STOP_OBUF/STOP_OBUF_CLKF__$INT 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ADR<9>               X..XXXXX.XXX.XX......................... 11      11
ADR<5>               X..XXXX......XX......................... 7       7
ADR<8>               X..XXXXX.XX..XX......................... 10      10
ADR<6>               X..XXXX..X...XX......................... 8       8
ADR<13>              XXXXXXXXXXXXXXX......................... 15      15
ADR<12>              XXXXXXXX.XXXXXX......................... 14      14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   11    I/O     I
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
XLXI_67/Q<8>          1       0     0   4     FB3_5   12    I/O     I
XLXI_67/Q<6>          1       0     0   4     FB3_6         (b)     (b)
XLXI_67/Q<5>          1       0     0   4     FB3_7         (b)     (b)
XLXI_67/Q<3>          1       0     0   4     FB3_8   13    I/O     (b)
ADR<15>               3       0     0   2     FB3_9   14    I/O     I/O
XLXI_67/Q<2>          1       0     0   4     FB3_10        (b)     (b)
AD_CLK                4       0     0   1     FB3_11  18    I/O     O
XLXI_67/Q<1>          1       0     0   4     FB3_12        (b)     (b)
XLXI_67/Q<0>          0       0     0   5     FB3_13        (b)     (b)
Teiler<7>             1       0     0   4     FB3_14  19    I/O     (b)
CS                    0       0     0   5     FB3_15  20    I/O     O
Teiler<4>             1       0     0   4     FB3_16        (b)     (b)
WE                    4       0     0   1     FB3_17  22    I/O     O
STOP_OBUF/STOP_OBUF_CLKF__$INT
                      5       0     0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ADR<0>.PIN        12: ADR<6>.PIN        23: STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK 
  2: ADR<10>.PIN       13: ADR<7>.PIN        24: Teiler<4>.LFBK 
  3: ADR<11>.PIN       14: ADR<8>.PIN        25: Teiler<7>.LFBK 
  4: ADR<12>.PIN       15: ADR<9>.PIN        26: Teiler<9> 
  5: ADR<13>.PIN       16: ADR_15_OBUF.LFBK  27: XLXI_67/Q<0>.LFBK 
  6: ADR<14>.PIN       17: CLK               28: XLXI_67/Q<1>.LFBK 
  7: ADR<1>.PIN        18: DIV0              29: XLXI_67/Q<2>.LFBK 
  8: ADR<2>.PIN        19: DIV1              30: XLXI_67/Q<3>.LFBK 
  9: ADR<3>.PIN        20: M50               31: XLXI_67/Q<5>.LFBK 
 10: ADR<4>.PIN        21: RESET             32: XLXI_67/Q<6>.LFBK 
 11: ADR<5>.PIN        22: RUN              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXI_67/Q<8>         .......................XX.XXXXXX........ 8       8
XLXI_67/Q<6>         .......................X..XXXXX......... 6       6
XLXI_67/Q<5>         .......................X..XXXX.......... 5       5
XLXI_67/Q<3>         ..........................XXX........... 3       3
ADR<15>              XXXXXXXXXXXXXXX.....X.X................. 17      17
XLXI_67/Q<2>         ..........................XX............ 2       2
AD_CLK               .................XXX...XXX.............. 6       6
XLXI_67/Q<1>         ..........................X............. 1       1
XLXI_67/Q<0>         ........................................ 0       0
Teiler<7>            .......................X..XXXXXX........ 7       7
CS                   ........................................ 0       0
Teiler<4>            ..........................XXXX.......... 4       4
WE                   ...............X.XXX.X.XXX.............. 8       8
STOP_OBUF/STOP_OBUF_CLKF__$INT 
                     ...............XXXXX.X.XXX.............. 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
OE                    5       0     0   0     FB4_2   24    I/O     O
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
ADR<0>                2       0     0   3     FB4_5   25    I/O     I/O
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
ADR<1>                3       0     0   2     FB4_8   26    I/O     I/O
ADR<10>               3       0     0   2     FB4_9   27    I/O     I/O
(unused)              0       0     0   5     FB4_10        (b)     
ADR<2>                3       0     0   2     FB4_11  28    I/O     I/O
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
ADR<3>                3       0     0   2     FB4_14  29    I/O     I/O
ADR<11>               3       0     0   2     FB4_15  33    I/O     I/O
(unused)              0       0     0   5     FB4_16        (b)     
ADR<4>                3       0     0   2     FB4_17  34    I/O     I/O
Teiler<9>             1       0     0   4     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ADR<15>.PIN       11: ADR_3_OBUF.LFBK                 21: Teiler<7> 
  2: ADR<5>.PIN        12: ADR_4_OBUF.LFBK                 22: Teiler<9>.LFBK 
  3: ADR<6>.PIN        13: CLK                             23: XLXI_67/Q<0> 
  4: ADR<7>.PIN        14: DIV0                            24: XLXI_67/Q<1> 
  5: ADR<8>.PIN        15: DIV1                            25: XLXI_67/Q<2> 
  6: ADR<9>.PIN        16: M50                             26: XLXI_67/Q<3> 
  7: ADR_0_OBUF.LFBK   17: RESET                           27: XLXI_67/Q<5> 
  8: ADR_10_OBUF.LFBK  18: RUN                             28: XLXI_67/Q<6> 
  9: ADR_1_OBUF.LFBK   19: STOP_OBUF/STOP_OBUF_CLKF__$INT  29: XLXI_67/Q<8> 
 10: ADR_2_OBUF.LFBK   20: Teiler<4>                      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
OE                   X...........XXXX.X.XXX.................. 9       9
ADR<0>               ................X.X..................... 2       2
ADR<1>               ......X.........X.X..................... 3       3
ADR<10>              .XXXXXX.XXXX....X.X..................... 12      12
ADR<2>               ......X.X.......X.X..................... 4       4
ADR<3>               ......X.XX......X.X..................... 5       5
ADR<11>              .XXXXXXXXXXX....X.X..................... 13      13
ADR<4>               ......X.XXX.....X.X..................... 6       6
Teiler<9>            ...................XX.XXXXXXX........... 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_ADR0: FTCPE port map (ADR(0),'1',NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');

FTCPE_ADR1: FTCPE port map (ADR(1),ADR_0_OBUF.LFBK,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');

FTCPE_ADR2: FTCPE port map (ADR(2),ADR_T(2),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(2) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK);

FTCPE_ADR3: FTCPE port map (ADR(3),ADR_T(3),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(3) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK AND 
	ADR_2_OBUF.LFBK);

FTCPE_ADR4: FTCPE port map (ADR(4),ADR_T(4),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(4) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK AND 
	ADR_2_OBUF.LFBK AND ADR_3_OBUF.LFBK);

FTCPE_ADR5: FTCPE port map (ADR(5),ADR_T(5),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(5) <= (ADR(0).PIN AND ADR(4).PIN AND ADR(1).PIN AND 
	ADR(2).PIN AND ADR(3).PIN);

FTCPE_ADR6: FTCPE port map (ADR(6),ADR_T(6),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(6) <= (ADR_5_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND 
	ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN);

FTCPE_ADR7: FTCPE port map (ADR(7),ADR_T(7),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(7) <= (ADR(0).PIN AND ADR(4).PIN AND ADR(1).PIN AND 
	ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(3).PIN);

FTCPE_ADR8: FTCPE port map (ADR(8),ADR_T(8),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(8) <= (ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR(0).PIN AND 
	ADR(4).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN AND 
	ADR(7).PIN);

FTCPE_ADR9: FTCPE port map (ADR(9),ADR_T(9),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(9) <= (ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND 
	ADR_8_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(1).PIN AND 
	ADR(2).PIN AND ADR(3).PIN AND ADR(7).PIN);

FTCPE_ADR10: FTCPE port map (ADR(10),ADR_T(10),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(10) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK AND 
	ADR_2_OBUF.LFBK AND ADR_3_OBUF.LFBK AND ADR_4_OBUF.LFBK AND ADR(8).PIN AND 
	ADR(5).PIN AND ADR(9).PIN AND ADR(6).PIN AND ADR(7).PIN);

FTCPE_ADR11: FTCPE port map (ADR(11),ADR_T(11),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(11) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK AND 
	ADR_2_OBUF.LFBK AND ADR_3_OBUF.LFBK AND ADR_4_OBUF.LFBK AND 
	ADR_10_OBUF.LFBK AND ADR(8).PIN AND ADR(5).PIN AND ADR(9).PIN AND 
	ADR(6).PIN AND ADR(7).PIN);

FTCPE_ADR12: FTCPE port map (ADR(12),ADR_T(12),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(12) <= (ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND 
	ADR_8_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND 
	ADR(1).PIN AND ADR(10).PIN AND ADR(2).PIN AND ADR(11).PIN AND 
	ADR(3).PIN AND ADR(7).PIN);

FTCPE_ADR13: FTCPE port map (ADR(13),ADR_T(13),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(13) <= (ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND 
	ADR_8_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR_12_OBUF.LFBK AND ADR(0).PIN AND 
	ADR(4).PIN AND ADR(1).PIN AND ADR(10).PIN AND ADR(2).PIN AND 
	ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN);

FTCPE_ADR14: FTCPE port map (ADR(14),ADR_T(14),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(14) <= (ADR_7_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND 
	ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND 
	ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND 
	ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN);

FTCPE_ADR15: FTCPE port map (ADR(15),ADR_T(15),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,RESET,'0');
ADR_T(15) <= (ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND 
	ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND 
	ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND 
	ADR(11).PIN AND ADR(14).PIN AND ADR(3).PIN AND ADR(7).PIN);


AD_CLK <= ((M50 AND NOT DIV1 AND NOT DIV0)
	OR (Teiler(9) AND DIV1 AND DIV0)
	OR (DIV1 AND NOT DIV0 AND Teiler(7).LFBK)
	OR (NOT DIV1 AND DIV0 AND Teiler(4).LFBK));


CS <= '0';


OE <= ((NOT CLK)
	OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN)
	OR (NOT Teiler(4) AND NOT DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN)
	OR (NOT Teiler(7) AND DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN)
	OR (DIV1 AND DIV0 AND RUN AND NOT Teiler(9).LFBK AND 
	NOT ADR(15).PIN));

FDCPE_STOP: FDCPE port map (STOP,STOP_D,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,'0',RESET);
STOP_D <= ADR(15).PIN
	 XOR 
STOP_D <= (ADR_7_OBUF.LFBK AND ADR_14_OBUF.LFBK AND ADR(0).PIN AND 
	ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND 
	ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND 
	ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN);


STOP_OBUF/STOP_OBUF_CLKF__$INT <= ((CLK)
	OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK)
	OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND 
	NOT ADR_15_OBUF.LFBK)
	OR (DIV1 AND NOT DIV0 AND RUN AND NOT Teiler(7).LFBK AND 
	NOT ADR_15_OBUF.LFBK)
	OR (NOT DIV1 AND DIV0 AND RUN AND NOT Teiler(4).LFBK AND 
	NOT ADR_15_OBUF.LFBK));

FTCPE_Teiler4: FTCPE port map (Teiler(4),Teiler_T(4),M50,'0','0');
Teiler_T(4) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK);

FTCPE_Teiler7: FTCPE port map (Teiler(7),Teiler_T(7),M50,'0','0');
Teiler_T(7) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND 
	XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK);

FTCPE_Teiler9: FTCPE port map (Teiler(9),Teiler_T(9),M50,'0','0');
Teiler_T(9) <= (Teiler(4) AND XLXI_67/Q(0) AND XLXI_67/Q(1) AND 
	XLXI_67/Q(5) AND Teiler(7) AND XLXI_67/Q(2) AND XLXI_67/Q(6) AND 
	XLXI_67/Q(3) AND XLXI_67/Q(8));


WE <= NOT (((NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK)
	OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND 
	NOT ADR_15_OBUF.LFBK)
	OR (DIV1 AND NOT DIV0 AND RUN AND NOT Teiler(7).LFBK AND 
	NOT ADR_15_OBUF.LFBK)
	OR (NOT DIV1 AND DIV0 AND RUN AND NOT Teiler(4).LFBK AND 
	NOT ADR_15_OBUF.LFBK)));

FTCPE_XLXI_67/Q0: FTCPE port map (XLXI_67/Q(0),'1',M50,'0','0');

FTCPE_XLXI_67/Q1: FTCPE port map (XLXI_67/Q(1),XLXI_67/Q(0).LFBK,M50,'0','0');

FTCPE_XLXI_67/Q2: FTCPE port map (XLXI_67/Q(2),XLXI_67/Q_T(2),M50,'0','0');
XLXI_67/Q_T(2) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK);

FTCPE_XLXI_67/Q3: FTCPE port map (XLXI_67/Q(3),XLXI_67/Q_T(3),M50,'0','0');
XLXI_67/Q_T(3) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK);

FTCPE_XLXI_67/Q5: FTCPE port map (XLXI_67/Q(5),XLXI_67/Q_T(5),M50,'0','0');
XLXI_67/Q_T(5) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK);

FTCPE_XLXI_67/Q6: FTCPE port map (XLXI_67/Q(6),XLXI_67/Q_T(6),M50,'0','0');
XLXI_67/Q_T(6) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND 
	XLXI_67/Q(5).LFBK);

FTCPE_XLXI_67/Q8: FTCPE port map (XLXI_67/Q(8),XLXI_67/Q_T(8),M50,'0','0');
XLXI_67/Q_T(8) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND 
	XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND 
	XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK AND Teiler(7).LFBK);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-15-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572-15-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ADR<7>                           23 GND                           
  2 ADR<14>                          24 OE                            
  3 RESET                            25 ADR<0>                        
  4 RUN                              26 ADR<1>                        
  5 M50                              27 ADR<10>                       
  6 TIE                              28 ADR<2>                        
  7 TIE                              29 ADR<3>                        
  8 STOP                             30 TDO                           
  9 CLK                              31 GND                           
 10 GND                              32 VCC                           
 11 DIV0                             33 ADR<11>                       
 12 DIV1                             34 ADR<4>                        
 13 TIE                              35 ADR<9>                        
 14 ADR<15>                          36 ADR<5>                        
 15 TDI                              37 ADR<8>                        
 16 TMS                              38 ADR<6>                        
 17 TCK                              39 TIE                           
 18 AD_CLK                           40 TIE                           
 19 TIE                              41 VCC                           
 20 CS                               42 TIE                           
 21 VCC                              43 ADR<13>                       
 22 WE                               44 ADR<12>                       


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-15-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25