$OpTx$INV$1__$INT <= ((NOT XLXN_286(6) AND NOT XLXN_286(7) AND NOT XLXN_286(8)) OR (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)) OR (XLXN_335(4) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7) AND XLXN_335(8))); |
FTCPE_CLK8MHz: FTCPE port map (CLK8MHz,XLXI_22/Q0,CLK_IN,CLK8MHz,'0'); |
HSync <= (XLXN_335(4) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7) AND XLXN_335(8)); |
VSync <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXI_101/Q0: FTCPE port map (XLXI_101/Q(0),'1',CLK8MHz,'0','0'); |
FTCPE_XLXI_101/Q1: FTCPE port map (XLXI_101/Q(1),XLXI_101/Q(0),CLK8MHz,'0','0'); |
FTCPE_XLXI_101/Q2: FTCPE port map (XLXI_101/Q(2),XLXI_101/Q_T(2),CLK8MHz,'0','0'); XLXI_101/Q_T(2) <= (XLXI_101/Q(0) AND XLXI_101/Q(1)); |
FTCPE_XLXI_101/Q3: FTCPE port map (XLXI_101/Q(3),XLXI_101/Q_T(3),CLK8MHz,'0','0'); XLXI_101/Q_T(3) <= (XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2)); |
FTCPE_XLXI_22/Q0: FTCPE port map (XLXI_22/Q0,'1',CLK_IN,CLK8MHz,'0'); |
FTCPE_XLXI_79/Q0: FTCPE port map (XLXI_79/Q(0),'1',XLXI_79/Q_C(0),'0','0'); XLXI_79/Q_C(0) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_2864: FTCPE port map (XLXN_286(4),XLXN_286_T(4),CLK8MHz,'0','0'); XLXN_286_T(4) <= (XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); |
FTCPE_XLXN_2865: FTCPE port map (XLXN_286(5),XLXN_286_T(5),CLK8MHz,'0','0'); XLXN_286_T(5) <= (XLXN_286(4) AND XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); |
FTCPE_XLXN_2866: FTCPE port map (XLXN_286(6),XLXN_286_T(6),CLK8MHz,'0','0'); XLXN_286_T(6) <= (XLXN_286(4) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); |
FTCPE_XLXN_2867: FTCPE port map (XLXN_286(7),XLXN_286_T(7),CLK8MHz,'0','0'); XLXN_286_T(7) <= (XLXN_286(4) AND XLXN_286(6) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); |
FTCPE_XLXN_2868: FTCPE port map (XLXN_286(8),XLXN_286_T(8),CLK8MHz,'0','0'); XLXN_286_T(8) <= (XLXN_286(4) AND XLXN_286(6) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXN_286(7) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); |
FTCPE_XLXN_3351: FTCPE port map (XLXN_335(1),XLXI_79/Q(0),XLXN_335_C(1),'0','0'); XLXN_335_C(1) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3352: FTCPE port map (XLXN_335(2),XLXN_335_T(2),XLXN_335_C(2),'0','0'); XLXN_335_T(2) <= (XLXI_79/Q(0) AND XLXN_335(1)); XLXN_335_C(2) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3353: FTCPE port map (XLXN_335(3),XLXN_335_T(3),XLXN_335_C(3),'0','0'); XLXN_335_T(3) <= (XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2)); XLXN_335_C(3) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3354: FTCPE port map (XLXN_335(4),XLXN_335_T(4),XLXN_335_C(4),'0','0'); XLXN_335_T(4) <= (XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(4) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3355: FTCPE port map (XLXN_335(5),XLXN_335_T(5),XLXN_335_C(5),'0','0'); XLXN_335_T(5) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(5) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3356: FTCPE port map (XLXN_335(6),XLXN_335_T(6),XLXN_335_C(6),'0','0'); XLXN_335_T(6) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(6) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3357: FTCPE port map (XLXN_335(7),XLXN_335_T(7),XLXN_335_C(7),'0','0'); XLXN_335_T(7) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3)); XLXN_335_C(7) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
FTCPE_XLXN_3358: FTCPE port map (XLXN_335(8),XLXN_335_T(8),XLXN_335_C(8),'0','0'); XLXN_335_T(8) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7)); XLXN_335_C(8) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); |
Red_0_I <= ((XLXN_382.EXP) OR (XLXN_383 AND XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_286(8)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(4) AND XLXN_335(4))); Red_0 <= Red_0_I when Red_0_OE = '1' else 'Z'; Red_0_OE <= NOT $OpTx$INV$1__$INT; |
Green_0_I <= ((XLXN_383 AND NOT XLXN_381) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_286(4) AND XLXN_335(4)) OR (XLXN_383 AND NOT XLXN_382 AND NOT XLXN_286(4) AND NOT XLXN_335(4)) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(7))); Green_0 <= Green_0_I when Green_0_OE = '1' else 'Z'; Green_0_OE <= NOT $OpTx$INV$1__$INT; |
Blue_0_I <= ((XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(6)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(4) AND XLXN_335(4)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND NOT XLXN_286(4) AND NOT XLXN_335(4))); Blue_0 <= Blue_0_I when Blue_0_OE = '1' else 'Z'; Blue_0_OE <= NOT $OpTx$INV$1__$INT; |
FTCPE_XLXN_381: FTCPE port map (XLXN_381,XLXN_381_T,Taster,XLXN_381_CLR,'0'); XLXN_381_T <= (XLXN_383 AND XLXN_382); XLXN_381_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); |
FTCPE_XLXN_382: FTCPE port map (XLXN_382,XLXN_383,Taster,XLXN_382_CLR,'0'); XLXN_382_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); |
FTCPE_XLXN_383: FTCPE port map (XLXN_383,'1',Taster,XLXN_383_CLR,'0'); XLXN_383_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); |
Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |