cpldfit: version J.30 Xilinx Inc. Fitter Report Design Name: Video Date: 5- 5-2007, 7:06PM Device Used: XC9536-15-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 29 /36 ( 81%) 66 /180 ( 37%) 38 /72 ( 53%) 23 /36 ( 64%) 7 /34 ( 21%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 13/18 15/36 15 30/90 1/17 FB2 16/18 23/36 23 36/90 4/17 ----- ----- ----- ----- 29/36 38/72 66/180 5/34 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_IN' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 1 1 | I/O : 6 28 Output : 5 5 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 7 7 ** Power Data ** There are 29 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 5 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State Red_0 6 7 FB1_17 24 I/O O STD FAST HSync 1 8 FB2_14 28 I/O O STD FAST VSync 1 5 FB2_15 27 I/O O STD FAST Blue_0 5 7 FB2_16 26 I/O O STD FAST Green_0 5 7 FB2_17 25 I/O O STD FAST ** 24 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXI_22/Q0 1 1 FB1_6 STD RESET XLXI_101/Q<0> 1 1 FB1_7 STD RESET XLXN_383 2 4 FB1_8 STD RESET XLXN_286<6> 2 7 FB1_9 STD RESET XLXN_286<5> 2 6 FB1_10 STD RESET XLXN_286<4> 2 5 FB1_11 STD RESET XLXI_101/Q<3> 2 4 FB1_12 STD RESET XLXI_101/Q<2> 2 3 FB1_13 STD RESET XLXI_101/Q<1> 2 2 FB1_14 STD RESET CLK8MHz 2 2 FB1_15 STD RESET XLXN_382 3 4 FB1_16 STD RESET XLXN_381 3 4 FB1_18 STD RESET XLXI_79/Q<0> 1 5 FB2_3 STD RESET XLXN_335<8> 2 13 FB2_4 STD RESET XLXN_335<7> 2 12 FB2_5 STD RESET XLXN_335<6> 2 11 FB2_6 STD RESET XLXN_335<5> 2 10 FB2_7 STD RESET XLXN_335<4> 2 9 FB2_8 STD RESET XLXN_335<3> 2 8 FB2_9 STD RESET XLXN_335<2> 2 7 FB2_10 STD RESET XLXN_335<1> 2 6 FB2_11 STD RESET XLXN_286<8> 2 9 FB2_12 STD RESET XLXN_286<7> 2 8 FB2_13 STD RESET $OpTx$INV$1__$INT 3 13 FB2_18 STD ** 2 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_IN FB1_3 5 GCK/I/O GCK Taster FB2_10 35 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 15/21 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 2 I/O (unused) 0 0 0 5 FB1_2 3 I/O (unused) 0 0 0 5 FB1_3 5 GCK/I/O GCK (unused) 0 0 0 5 FB1_4 4 I/O (unused) 0 0 0 5 FB1_5 6 GCK/I/O XLXI_22/Q0 1 0 0 4 FB1_6 8 I/O (b) XLXI_101/Q<0> 1 0 0 4 FB1_7 7 GCK/I/O (b) XLXN_383 2 0 0 3 FB1_8 9 I/O (b) XLXN_286<6> 2 0 0 3 FB1_9 11 I/O (b) XLXN_286<5> 2 0 0 3 FB1_10 12 I/O (b) XLXN_286<4> 2 0 0 3 FB1_11 13 I/O (b) XLXI_101/Q<3> 2 0 0 3 FB1_12 14 I/O (b) XLXI_101/Q<2> 2 0 0 3 FB1_13 18 I/O (b) XLXI_101/Q<1> 2 0 0 3 FB1_14 19 I/O (b) CLK8MHz 2 0 0 3 FB1_15 20 I/O (b) XLXN_382 3 0 \/1 1 FB1_16 22 I/O (b) Red_0 6 1<- 0 0 FB1_17 24 I/O O XLXN_381 3 0 0 2 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$INV$1__$INT 6: XLXI_101/Q<2> 11: XLXN_286<8> 2: CLK8MHz 7: XLXI_101/Q<3> 12: XLXN_335<4> 3: Taster 8: XLXI_22/Q0 13: XLXN_381 4: XLXI_101/Q<0> 9: XLXN_286<4> 14: XLXN_382 5: XLXI_101/Q<1> 10: XLXN_286<5> 15: XLXN_383 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXI_22/Q0 .X...................................... 1 1 XLXI_101/Q<0> .X...................................... 1 1 XLXN_383 ..X.........XXX......................... 4 4 XLXN_286<6> .X.XXXX.XX.............................. 7 7 XLXN_286<5> .X.XXXX.X............................... 6 6 XLXN_286<4> .X.XXXX................................. 5 5 XLXI_101/Q<3> .X.XXX.................................. 4 4 XLXI_101/Q<2> .X.XX................................... 3 3 XLXI_101/Q<1> .X.X.................................... 2 2 CLK8MHz .X.....X................................ 2 2 XLXN_382 ..X.........XXX......................... 4 4 Red_0 X.......X.XXXXX......................... 7 7 XLXN_381 ..X.........XXX......................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 23/13 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 1 I/O (unused) 0 0 0 5 FB2_2 44 I/O XLXI_79/Q<0> 1 0 0 4 FB2_3 42 GTS/I/O (b) XLXN_335<8> 2 0 0 3 FB2_4 43 I/O (b) XLXN_335<7> 2 0 0 3 FB2_5 40 GTS/I/O (b) XLXN_335<6> 2 0 0 3 FB2_6 39 GSR/I/O (b) XLXN_335<5> 2 0 0 3 FB2_7 38 I/O (b) XLXN_335<4> 2 0 0 3 FB2_8 37 I/O (b) XLXN_335<3> 2 0 0 3 FB2_9 36 I/O (b) XLXN_335<2> 2 0 0 3 FB2_10 35 I/O I XLXN_335<1> 2 0 0 3 FB2_11 34 I/O (b) XLXN_286<8> 2 0 0 3 FB2_12 33 I/O (b) XLXN_286<7> 2 0 0 3 FB2_13 29 I/O (b) HSync 1 0 0 4 FB2_14 28 I/O O VSync 1 0 0 4 FB2_15 27 I/O O Blue_0 5 0 0 0 FB2_16 26 I/O O Green_0 5 0 0 0 FB2_17 25 I/O O $OpTx$INV$1__$INT 3 0 0 2 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$INV$1__$INT 9: XLXN_286<5> 17: XLXN_335<5> 2: CLK8MHz 10: XLXN_286<6> 18: XLXN_335<6> 3: XLXI_101/Q<0> 11: XLXN_286<7> 19: XLXN_335<7> 4: XLXI_101/Q<1> 12: XLXN_286<8> 20: XLXN_335<8> 5: XLXI_101/Q<2> 13: XLXN_335<1> 21: XLXN_381 6: XLXI_101/Q<3> 14: XLXN_335<2> 22: XLXN_382 7: XLXI_79/Q<0> 15: XLXN_335<3> 23: XLXN_383 8: XLXN_286<4> 16: XLXN_335<4> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXI_79/Q<0> .......XXXXX............................ 5 5 XLXN_335<8> ......XXXXXXXXXXXXX..................... 13 13 XLXN_335<7> ......XXXXXXXXXXXX...................... 12 12 XLXN_335<6> ......XXXXXXXXXXX....................... 11 11 XLXN_335<5> ......XXXXXXXXXX........................ 10 10 XLXN_335<4> ......XXXXXXXXX......................... 9 9 XLXN_335<3> ......XXXXXXXX.......................... 8 8 XLXN_335<2> ......XXXXXXX........................... 7 7 XLXN_335<1> ......XXXXXX............................ 6 6 XLXN_286<8> .XXXXX.XXXX............................. 9 9 XLXN_286<7> .XXXXX.XXX.............................. 8 8 HSync ............XXXXXXXX.................... 8 8 VSync .......XXXXX............................ 5 5 Blue_0 X......X.X.....X....XXX................. 7 7 Green_0 X......X..X....X....XXX................. 7 7 $OpTx$INV$1__$INT .......XXXXXXXXXXXXX.................... 13 13 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$INV$1__$INT <= ((NOT XLXN_286(6) AND NOT XLXN_286(7) AND NOT XLXN_286(8)) OR (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)) OR (XLXN_335(4) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7) AND XLXN_335(8))); Blue_0_I <= ((XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(6)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(4) AND XLXN_335(4)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND NOT XLXN_286(4) AND NOT XLXN_335(4))); Blue_0 <= Blue_0_I when Blue_0_OE = '1' else 'Z'; Blue_0_OE <= NOT $OpTx$INV$1__$INT; FTCPE_CLK8MHz: FTCPE port map (CLK8MHz,XLXI_22/Q0,CLK_IN,CLK8MHz,'0'); Green_0_I <= ((XLXN_383 AND NOT XLXN_381) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_286(4) AND XLXN_335(4)) OR (XLXN_383 AND NOT XLXN_382 AND NOT XLXN_286(4) AND NOT XLXN_335(4)) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(7))); Green_0 <= Green_0_I when Green_0_OE = '1' else 'Z'; Green_0_OE <= NOT $OpTx$INV$1__$INT; HSync <= (XLXN_335(4) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7) AND XLXN_335(8)); Red_0_I <= ((XLXN_382.EXP) OR (XLXN_383 AND XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND NOT XLXN_381) OR (NOT XLXN_383 AND NOT XLXN_382 AND XLXN_286(8)) OR (XLXN_383 AND NOT XLXN_382 AND XLXN_381 AND XLXN_286(4) AND XLXN_335(4))); Red_0 <= Red_0_I when Red_0_OE = '1' else 'Z'; Red_0_OE <= NOT $OpTx$INV$1__$INT; VSync <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXI_101/Q0: FTCPE port map (XLXI_101/Q(0),'1',CLK8MHz,'0','0'); FTCPE_XLXI_101/Q1: FTCPE port map (XLXI_101/Q(1),XLXI_101/Q(0),CLK8MHz,'0','0'); FTCPE_XLXI_101/Q2: FTCPE port map (XLXI_101/Q(2),XLXI_101/Q_T(2),CLK8MHz,'0','0'); XLXI_101/Q_T(2) <= (XLXI_101/Q(0) AND XLXI_101/Q(1)); FTCPE_XLXI_101/Q3: FTCPE port map (XLXI_101/Q(3),XLXI_101/Q_T(3),CLK8MHz,'0','0'); XLXI_101/Q_T(3) <= (XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2)); FTCPE_XLXI_22/Q0: FTCPE port map (XLXI_22/Q0,'1',CLK_IN,CLK8MHz,'0'); FTCPE_XLXI_79/Q0: FTCPE port map (XLXI_79/Q(0),'1',XLXI_79/Q_C(0),'0','0'); XLXI_79/Q_C(0) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_2864: FTCPE port map (XLXN_286(4),XLXN_286_T(4),CLK8MHz,'0','0'); XLXN_286_T(4) <= (XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); FTCPE_XLXN_2865: FTCPE port map (XLXN_286(5),XLXN_286_T(5),CLK8MHz,'0','0'); XLXN_286_T(5) <= (XLXN_286(4) AND XLXI_101/Q(0) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); FTCPE_XLXN_2866: FTCPE port map (XLXN_286(6),XLXN_286_T(6),CLK8MHz,'0','0'); XLXN_286_T(6) <= (XLXN_286(4) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); FTCPE_XLXN_2867: FTCPE port map (XLXN_286(7),XLXN_286_T(7),CLK8MHz,'0','0'); XLXN_286_T(7) <= (XLXN_286(4) AND XLXN_286(6) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); FTCPE_XLXN_2868: FTCPE port map (XLXN_286(8),XLXN_286_T(8),CLK8MHz,'0','0'); XLXN_286_T(8) <= (XLXN_286(4) AND XLXN_286(6) AND XLXI_101/Q(0) AND XLXN_286(5) AND XLXN_286(7) AND XLXI_101/Q(1) AND XLXI_101/Q(2) AND XLXI_101/Q(3)); FTCPE_XLXN_3351: FTCPE port map (XLXN_335(1),XLXI_79/Q(0),XLXN_335_C(1),'0','0'); XLXN_335_C(1) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3352: FTCPE port map (XLXN_335(2),XLXN_335_T(2),XLXN_335_C(2),'0','0'); XLXN_335_T(2) <= (XLXI_79/Q(0) AND XLXN_335(1)); XLXN_335_C(2) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3353: FTCPE port map (XLXN_335(3),XLXN_335_T(3),XLXN_335_C(3),'0','0'); XLXN_335_T(3) <= (XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2)); XLXN_335_C(3) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3354: FTCPE port map (XLXN_335(4),XLXN_335_T(4),XLXN_335_C(4),'0','0'); XLXN_335_T(4) <= (XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(4) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3355: FTCPE port map (XLXN_335(5),XLXN_335_T(5),XLXN_335_C(5),'0','0'); XLXN_335_T(5) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(5) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3356: FTCPE port map (XLXN_335(6),XLXN_335_T(6),XLXN_335_C(6),'0','0'); XLXN_335_T(6) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(3)); XLXN_335_C(6) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3357: FTCPE port map (XLXN_335(7),XLXN_335_T(7),XLXN_335_C(7),'0','0'); XLXN_335_T(7) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3)); XLXN_335_C(7) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_3358: FTCPE port map (XLXN_335(8),XLXN_335_T(8),XLXN_335_C(8),'0','0'); XLXN_335_T(8) <= (XLXN_335(4) AND XLXI_79/Q(0) AND XLXN_335(1) AND XLXN_335(5) AND XLXN_335(2) AND XLXN_335(6) AND XLXN_335(3) AND XLXN_335(7)); XLXN_335_C(8) <= (XLXN_286(4) AND XLXN_286(6) AND XLXN_286(5) AND XLXN_286(7) AND XLXN_286(8)); FTCPE_XLXN_381: FTCPE port map (XLXN_381,XLXN_381_T,Taster,XLXN_381_CLR,'0'); XLXN_381_T <= (XLXN_383 AND XLXN_382); XLXN_381_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); FTCPE_XLXN_382: FTCPE port map (XLXN_382,XLXN_383,Taster,XLXN_382_CLR,'0'); XLXN_382_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); FTCPE_XLXN_383: FTCPE port map (XLXN_383,'1',Taster,XLXN_383_CLR,'0'); XLXN_383_CLR <= (XLXN_383 AND XLXN_382 AND XLXN_381); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536-15-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9536-15-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 23 GND 2 TIE 24 Red_0 3 TIE 25 Green_0 4 TIE 26 Blue_0 5 CLK_IN 27 VSync 6 TIE 28 HSync 7 TIE 29 TIE 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 TIE 33 TIE 12 TIE 34 TIE 13 TIE 35 Taster 14 TIE 36 TIE 15 TDI 37 TIE 16 TMS 38 TIE 17 TCK 39 TIE 18 TIE 40 TIE 19 TIE 41 VCC 20 TIE 42 TIE 21 VCC 43 TIE 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536-15-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25