cpldfit: version I.31 Xilinx Inc. Fitter Report Design Name: graka Date: 9-16-2006, 1:06AM Device Used: XC9572-15-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 72 /72 (100%) 146 /360 ( 41%) 105/144 ( 73%) 43 /72 ( 60%) 47 /69 ( 68%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 18/18* 16/36 16 36/90 2/18 FB2 18/18* 32/36 32 40/90 13/17 FB3 18/18* 26/36 26 35/90 3/17 FB4 18/18* 31/36 31 35/90 17/17* ----- ----- ----- ----- 72/72 105/144 146/360 35/69 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_I' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 11 11 | I/O : 46 63 Output : 28 28 | GCK/IO : 1 3 Bidirectional : 7 7 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 47 47 ** Power Data ** There are 72 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld:908 - Converting I/O pin 'ExMemData<6>' to an output pin. The pin feedback is unused after optimization. Please verify functionality via simulation. WARNING:Cpld:908 - Converting I/O pin 'ExMemData<7>' to an output pin. The pin feedback is unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 35 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State RGB_O<4> 3 4 FB1_2 1 I/O O STD FAST RESET RGB_O<5> 3 4 FB1_5 2 I/O O STD FAST RESET AddrBus<5> 2 3 FB2_1 63 I/O O STD FAST AddrBus<13> 2 3 FB2_2 69 I/O O STD FAST AddrBus<8> 2 3 FB2_3 67 I/O O STD FAST AddrBus<7> 2 3 FB2_4 68 I/O O STD FAST AddrBus<12> 2 3 FB2_5 70 I/O O STD FAST WR_INV 3 5 FB2_6 71 I/O I/O STD FAST SET AddrBus<14> 2 3 FB2_8 72 I/O O STD FAST VSync 1 5 FB2_12 79 I/O O STD FAST HSync 1 8 FB2_13 80 I/O O STD FAST RGB_O<0> 3 4 FB2_14 81 I/O O STD FAST RESET RGB_O<2> 3 4 FB2_15 83 I/O O STD FAST RESET RGB_O<1> 3 4 FB2_16 82 I/O O STD FAST RESET RGB_O<3> 3 4 FB2_17 84 I/O O STD FAST RESET Addr15_INV 2 3 FB3_12 41 I/O O STD FAST ExMemData<3> 2 2 FB3_13 43 I/O I/O STD FAST ExMemData<4> 2 2 FB3_16 45 I/O I/O STD FAST ExMemData<1> 2 2 FB4_1 46 I/O I/O STD FAST ExMemData<2> 2 2 FB4_2 44 I/O I/O STD FAST AddrBus<0> 2 3 FB4_3 51 I/O O STD FAST ExMemData<7> 2 2 FB4_4 52 I/O O STD FAST ExMemData<5> 2 2 FB4_5 47 I/O I/O STD FAST AddrBus<15> 2 3 FB4_6 54 I/O O STD FAST AddrBus<2> 2 3 FB4_7 55 I/O O STD FAST ExMemData<0> 2 2 FB4_8 48 I/O I/O STD FAST ExMemData<6> 2 2 FB4_9 50 I/O O STD FAST AddrBus<3> 2 3 FB4_10 57 I/O O STD FAST AddrBus<1> 2 3 FB4_11 53 I/O O STD FAST RD_INV 1 1 FB4_12 58 I/O O STD FAST AddrBus<4> 2 3 FB4_13 61 I/O O STD FAST AddrBus<10> 2 3 FB4_14 56 I/O O STD FAST AddrBus<9> 2 3 FB4_15 65 I/O O STD FAST AddrBus<11> 2 3 FB4_16 62 I/O O STD FAST AddrBus<6> 2 3 FB4_17 66 I/O O STD FAST ** 37 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXN_311 1 1 FB1_1 STD RESET A<0> 1 2 FB1_3 STD RESET XLXN_363<8> 2 4 FB1_4 STD RESET XLXN_363<5> 2 4 FB1_6 STD RESET XLXN_363<4> 2 4 FB1_7 STD RESET XLXN_363<3> 2 4 FB1_8 STD RESET XLXN_363<2> 2 4 FB1_9 STD RESET XLXN_363<1> 2 4 FB1_10 STD RESET XLXN_363<13> 2 4 FB1_11 STD RESET XLXN_363<12> 2 4 FB1_12 STD RESET XLXN_363<11> 2 4 FB1_13 STD RESET XLXN_363<10> 2 4 FB1_14 STD RESET XLXN_363<0> 2 4 FB1_15 STD RESET XLXN_330 2 3 FB1_16 STD RESET XLXN_312 2 2 FB1_17 STD RESET A<1> 2 3 FB1_18 STD RESET XLXN_363<15> 2 4 FB2_7 STD RESET XLXN_363<14> 2 4 FB2_9 STD RESET XLXI_112/XLXI_127/XLXN_19<8> 2 13 FB2_10 STD RESET XLXI_112/XLXI_127/XLXN_19<7> 2 12 FB2_11 STD RESET XLXN_214/XLXN_214_D2__$INT 3 13 FB2_18 STD XLXI_112/XLXI_127/XLXI_1/Q<0> 1 5 FB3_1 STD RESET XLXN_363<9> 2 4 FB3_2 STD RESET XLXN_363<7> 2 4 FB3_3 STD RESET XLXI_112/XLXI_127/XLXN_19<6> 2 11 FB3_4 STD RESET XLXI_112/XLXI_127/XLXN_19<5> 2 10 FB3_5 STD RESET XLXI_112/XLXI_127/XLXN_19<4> 2 9 FB3_6 STD RESET XLXI_112/XLXI_127/XLXN_19<3> 2 8 FB3_7 STD RESET XLXI_112/XLXI_127/XLXN_19<2> 2 7 FB3_8 STD RESET XLXI_112/XLXI_127/XLXN_19<1> 2 6 FB3_9 STD RESET A<7> 2 9 FB3_10 STD RESET A<6> 2 8 FB3_11 STD RESET A<5> 2 7 FB3_14 STD RESET A<4> 2 6 FB3_15 STD RESET A<3> 2 5 FB3_17 STD RESET A<2> 2 4 FB3_18 STD RESET XLXN_363<6> 2 4 FB4_18 STD RESET ** 12 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use DATA<0> FB1_7 11 I/O I CLK_I FB1_9 9 GCK/I/O GCK DATA<1> FB1_10 13 I/O I DATA<4> FB1_12 18 I/O I DATA<6> FB1_13 20 I/O I DATA<2> FB1_15 14 I/O I A0 FB1_16 23 I/O I DATA<3> FB1_17 15 I/O I WR FB3_1 25 I/O I DATA<5> FB3_2 17 I/O I DATA<7> FB3_5 19 I/O I A1 FB3_8 21 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 16/20 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use XLXN_311 1 0 0 4 FB1_1 4 I/O (b) RGB_O<4> 3 0 0 2 FB1_2 1 I/O O A<0> 1 0 0 4 FB1_3 6 I/O (b) XLXN_363<8> 2 0 0 3 FB1_4 7 I/O (b) RGB_O<5> 3 0 0 2 FB1_5 2 I/O O XLXN_363<5> 2 0 0 3 FB1_6 3 I/O (b) XLXN_363<4> 2 0 0 3 FB1_7 11 I/O I XLXN_363<3> 2 0 0 3 FB1_8 5 I/O (b) XLXN_363<2> 2 0 0 3 FB1_9 9 GCK/I/O GCK XLXN_363<1> 2 0 0 3 FB1_10 13 I/O I XLXN_363<13> 2 0 0 3 FB1_11 10 GCK/I/O (b) XLXN_363<12> 2 0 0 3 FB1_12 18 I/O I XLXN_363<11> 2 0 0 3 FB1_13 20 I/O I XLXN_363<10> 2 0 0 3 FB1_14 12 GCK/I/O (b) XLXN_363<0> 2 0 0 3 FB1_15 14 I/O I XLXN_330 2 0 0 3 FB1_16 23 I/O I XLXN_312 2 0 0 3 FB1_17 15 I/O I A<1> 2 0 0 3 FB1_18 24 I/O (b) Signals Used by Logic in Function Block 1: A0 7: DATA<3> 12: WR 2: A1 8: DATA<4> 13: XLXN_214/XLXN_214_D2__$INT 3: A<0>.LFBK 9: DATA<5> 14: XLXN_311.LFBK 4: DATA<0> 10: ExMemData<5>.PIN 15: XLXN_312.LFBK 5: DATA<1> 11: ExMemData<4>.PIN 16: XLXN_330.LFBK 6: DATA<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXN_311 ...............X........................ 1 1 RGB_O<4> ..........X.XXX......................... 4 4 A<0> .............XX......................... 2 2 XLXN_363<8> XX.X.......X............................ 4 4 RGB_O<5> .........X..XXX......................... 4 4 XLXN_363<5> XX......X..X............................ 4 4 XLXN_363<4> XX.....X...X............................ 4 4 XLXN_363<3> XX....X....X............................ 4 4 XLXN_363<2> XX...X.....X............................ 4 4 XLXN_363<1> XX..X......X............................ 4 4 XLXN_363<13> XX......X..X............................ 4 4 XLXN_363<12> XX.....X...X............................ 4 4 XLXN_363<11> XX....X....X............................ 4 4 XLXN_363<10> XX...X.....X............................ 4 4 XLXN_363<0> XX.X.......X............................ 4 4 XLXN_330 .............XXX........................ 3 3 XLXN_312 .............X.X........................ 2 2 A<1> ..X..........XX......................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use AddrBus<5> 2 0 0 3 FB2_1 63 I/O O AddrBus<13> 2 0 0 3 FB2_2 69 I/O O AddrBus<8> 2 0 0 3 FB2_3 67 I/O O AddrBus<7> 2 0 0 3 FB2_4 68 I/O O AddrBus<12> 2 0 0 3 FB2_5 70 I/O O WR_INV 3 0 0 2 FB2_6 71 I/O I/O XLXN_363<15> 2 0 0 3 FB2_7 76 GTS/I/O (b) AddrBus<14> 2 0 0 3 FB2_8 72 I/O O XLXN_363<14> 2 0 0 3 FB2_9 74 GSR/I/O (b) XLXI_112/XLXI_127/XLXN_19<8> 2 0 0 3 FB2_10 75 I/O (b) XLXI_112/XLXI_127/XLXN_19<7> 2 0 0 3 FB2_11 77 GTS/I/O (b) VSync 1 0 0 4 FB2_12 79 I/O O HSync 1 0 0 4 FB2_13 80 I/O O RGB_O<0> 3 0 0 2 FB2_14 81 I/O O RGB_O<2> 3 0 0 2 FB2_15 83 I/O O RGB_O<1> 3 0 0 2 FB2_16 82 I/O O RGB_O<3> 3 0 0 2 FB2_17 84 I/O O XLXN_214/XLXN_214_D2__$INT 3 0 0 2 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: A0 12: ExMemData<1>.PIN 23: XLXI_112/XLXI_127/XLXN_19<8>.LFBK 2: A1 13: ExMemData<0>.PIN 24: XLXN_214/XLXN_214_D2__$INT.LFBK 3: A<3> 14: WR 25: XLXN_311 4: A<4> 15: XLXI_112/XLXI_127/XLXI_1/Q<0> 26: XLXN_312 5: A<5> 16: XLXI_112/XLXI_127/XLXN_19<1> 27: XLXN_363<12> 6: A<6> 17: XLXI_112/XLXI_127/XLXN_19<2> 28: XLXN_363<13> 7: A<7> 18: XLXI_112/XLXI_127/XLXN_19<3> 29: XLXN_363<14>.LFBK 8: DATA<6> 19: XLXI_112/XLXI_127/XLXN_19<4> 30: XLXN_363<5> 9: DATA<7> 20: XLXI_112/XLXI_127/XLXN_19<5> 31: XLXN_363<7> 10: ExMemData<3>.PIN 21: XLXI_112/XLXI_127/XLXN_19<6> 32: XLXN_363<8> 11: ExMemData<2>.PIN 22: XLXI_112/XLXI_127/XLXN_19<7>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AddrBus<5> ....X....................X...X.......... 3 3 AddrBus<13> ....................X....X.X............ 3 3 AddrBus<8> ...............X.........X.....X........ 3 3 AddrBus<7> ......X..................X....X......... 3 3 AddrBus<12> ...................X.....XX............. 3 3 WR_INV XX...........X..........XX.............. 5 5 XLXN_363<15> XX......X....X.......................... 4 4 AddrBus<14> .....................X...X..X........... 3 3 XLXN_363<14> XX.....X.....X.......................... 4 4 XLXI_112/XLXI_127/XLXN_19<8> ..XXXXX.......XXXXXXXX.................. 13 13 XLXI_112/XLXI_127/XLXN_19<7> ..XXXXX.......XXXXXXX................... 12 12 VSync ..XXXXX................................. 5 5 HSync ...............XXXXXXXX................. 8 8 RGB_O<0> ............X..........XXX.............. 4 4 RGB_O<2> ..........X............XXX.............. 4 4 RGB_O<1> ...........X...........XXX.............. 4 4 RGB_O<3> .........X.............XXX.............. 4 4 XLXN_214/XLXN_214_D2__$INT ..XXXXX........XXXXXXXX................. 13 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 26/10 Number of signals used by logic mapping into function block: 26 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use XLXI_112/XLXI_127/XLXI_1/Q<0> 1 0 0 4 FB3_1 25 I/O I XLXN_363<9> 2 0 0 3 FB3_2 17 I/O I XLXN_363<7> 2 0 0 3 FB3_3 31 I/O (b) XLXI_112/XLXI_127/XLXN_19<6> 2 0 0 3 FB3_4 32 I/O (b) XLXI_112/XLXI_127/XLXN_19<5> 2 0 0 3 FB3_5 19 I/O I XLXI_112/XLXI_127/XLXN_19<4> 2 0 0 3 FB3_6 34 I/O (b) XLXI_112/XLXI_127/XLXN_19<3> 2 0 0 3 FB3_7 35 I/O (b) XLXI_112/XLXI_127/XLXN_19<2> 2 0 0 3 FB3_8 21 I/O I XLXI_112/XLXI_127/XLXN_19<1> 2 0 0 3 FB3_9 26 I/O (b) A<7> 2 0 0 3 FB3_10 40 I/O (b) A<6> 2 0 0 3 FB3_11 33 I/O (b) Addr15_INV 2 0 0 3 FB3_12 41 I/O O ExMemData<3> 2 0 0 3 FB3_13 43 I/O I/O A<5> 2 0 0 3 FB3_14 36 I/O (b) A<4> 2 0 0 3 FB3_15 37 I/O (b) ExMemData<4> 2 0 0 3 FB3_16 45 I/O I/O A<3> 2 0 0 3 FB3_17 39 I/O (b) A<2> 2 0 0 3 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: A0 10: A<7>.LFBK 19: XLXI_112/XLXI_127/XLXN_19<2>.LFBK 2: A1 11: DATA<1> 20: XLXI_112/XLXI_127/XLXN_19<3>.LFBK 3: A<0> 12: DATA<3> 21: XLXI_112/XLXI_127/XLXN_19<4>.LFBK 4: A<1> 13: DATA<4> 22: XLXI_112/XLXI_127/XLXN_19<5>.LFBK 5: A<2>.LFBK 14: DATA<7> 23: XLXI_112/XLXI_127/XLXN_19<8> 6: A<3>.LFBK 15: WR 24: XLXN_311 7: A<4>.LFBK 16: WR_INV.PIN 25: XLXN_312 8: A<5>.LFBK 17: XLXI_112/XLXI_127/XLXI_1/Q<0>.LFBK 26: XLXN_363<15> 9: A<6>.LFBK 18: XLXI_112/XLXI_127/XLXN_19<1>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXI_112/XLXI_127/XLXI_1/Q<0> .....XXXXX.............................. 5 5 XLXN_363<9> XX........X...X......................... 4 4 XLXN_363<7> XX...........XX......................... 4 4 XLXI_112/XLXI_127/XLXN_19<6> .....XXXXX......XXXXXX.................. 11 11 XLXI_112/XLXI_127/XLXN_19<5> .....XXXXX......XXXXX................... 10 10 XLXI_112/XLXI_127/XLXN_19<4> .....XXXXX......XXXX.................... 9 9 XLXI_112/XLXI_127/XLXN_19<3> .....XXXXX......XXX..................... 8 8 XLXI_112/XLXI_127/XLXN_19<2> .....XXXXX......XX...................... 7 7 XLXI_112/XLXI_127/XLXN_19<1> .....XXXXX......X....................... 6 6 A<7> ..XXXXXXX..............XX............... 9 9 A<6> ..XXXXXX...............XX............... 8 8 Addr15_INV ......................X.XX.............. 3 3 ExMemData<3> ...........X...X........................ 2 2 A<5> ..XXXXX................XX............... 7 7 A<4> ..XXXX.................XX............... 6 6 ExMemData<4> ............X..X........................ 2 2 A<3> ..XXX..................XX............... 5 5 A<2> ..XX...................XX............... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ExMemData<1> 2 0 0 3 FB4_1 46 I/O I/O ExMemData<2> 2 0 0 3 FB4_2 44 I/O I/O AddrBus<0> 2 0 0 3 FB4_3 51 I/O O ExMemData<7> 2 0 0 3 FB4_4 52 I/O O ExMemData<5> 2 0 0 3 FB4_5 47 I/O I/O AddrBus<15> 2 0 0 3 FB4_6 54 I/O O AddrBus<2> 2 0 0 3 FB4_7 55 I/O O ExMemData<0> 2 0 0 3 FB4_8 48 I/O I/O ExMemData<6> 2 0 0 3 FB4_9 50 I/O O AddrBus<3> 2 0 0 3 FB4_10 57 I/O O AddrBus<1> 2 0 0 3 FB4_11 53 I/O O RD_INV 1 0 0 4 FB4_12 58 I/O O AddrBus<4> 2 0 0 3 FB4_13 61 I/O O AddrBus<10> 2 0 0 3 FB4_14 56 I/O O AddrBus<9> 2 0 0 3 FB4_15 65 I/O O AddrBus<11> 2 0 0 3 FB4_16 62 I/O O AddrBus<6> 2 0 0 3 FB4_17 66 I/O O XLXN_363<6> 2 0 0 3 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: A0 12: DATA<5> 22: XLXN_363<0> 2: A1 13: DATA<6> 23: XLXN_363<10> 3: A<0> 14: DATA<7> 24: XLXN_363<11> 4: A<1> 15: WR 25: XLXN_363<15> 5: A<2> 16: WR_INV.PIN 26: XLXN_363<1> 6: A<3> 17: XLXI_112/XLXI_127/XLXN_19<2> 27: XLXN_363<2> 7: A<4> 18: XLXI_112/XLXI_127/XLXN_19<3> 28: XLXN_363<3> 8: A<6> 19: XLXI_112/XLXI_127/XLXN_19<4> 29: XLXN_363<4> 9: DATA<0> 20: XLXI_112/XLXI_127/XLXN_19<8> 30: XLXN_363<6>.LFBK 10: DATA<1> 21: XLXN_312 31: XLXN_363<9> 11: DATA<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ExMemData<1> .........X.....X........................ 2 2 ExMemData<2> ..........X....X........................ 2 2 AddrBus<0> ..X.................XX.................. 3 3 ExMemData<7> .............X.X........................ 2 2 ExMemData<5> ...........X...X........................ 2 2 AddrBus<15> ...................XX...X............... 3 3 AddrBus<2> ....X...............X.....X............. 3 3 ExMemData<0> ........X......X........................ 2 2 ExMemData<6> ............X..X........................ 2 2 AddrBus<3> .....X..............X......X............ 3 3 AddrBus<1> ...X................X....X.............. 3 3 RD_INV ....................X................... 1 1 AddrBus<4> ......X.............X.......X........... 3 3 AddrBus<10> .................X..X.X................. 3 3 AddrBus<9> ................X...X.........X......... 3 3 AddrBus<11> ..................X.X..X................ 3 3 AddrBus<6> .......X............X........X.......... 3 3 XLXN_363<6> XX..........X.X......................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_A0: FTCPE port map (A(0),'1',A_C(0),'0','0'); A_C(0) <= (NOT XLXN_311.LFBK AND XLXN_312.LFBK); FTCPE_A1: FTCPE port map (A(1),A(0).LFBK,A_C(1),'0','0'); A_C(1) <= (NOT XLXN_311.LFBK AND XLXN_312.LFBK); FTCPE_A2: FTCPE port map (A(2),A_T(2),A_C(2),'0','0'); A_T(2) <= (A(0) AND A(1)); A_C(2) <= (NOT XLXN_311 AND XLXN_312); FTCPE_A3: FTCPE port map (A(3),A_T(3),A_C(3),'0','0'); A_T(3) <= (A(0) AND A(1) AND A(2).LFBK); A_C(3) <= (NOT XLXN_311 AND XLXN_312); FTCPE_A4: FTCPE port map (A(4),A_T(4),A_C(4),'0','0'); A_T(4) <= (A(0) AND A(1) AND A(3).LFBK AND A(2).LFBK); A_C(4) <= (NOT XLXN_311 AND XLXN_312); FTCPE_A5: FTCPE port map (A(5),A_T(5),A_C(5),'0','0'); A_T(5) <= (A(0) AND A(1) AND A(4).LFBK AND A(3).LFBK AND A(2).LFBK); A_C(5) <= (NOT XLXN_311 AND XLXN_312); FTCPE_A6: FTCPE port map (A(6),A_T(6),A_C(6),'0','0'); A_T(6) <= (A(0) AND A(1) AND A(4).LFBK AND A(5).LFBK AND A(3).LFBK AND A(2).LFBK); A_C(6) <= (NOT XLXN_311 AND XLXN_312); FTCPE_A7: FTCPE port map (A(7),A_T(7),A_C(7),'0','0'); A_T(7) <= (A(0) AND A(1) AND A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(2).LFBK); A_C(7) <= (NOT XLXN_311 AND XLXN_312); Addr15_INV <= NOT (((XLXN_312 AND XLXN_363(15)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(8)))); AddrBus(0) <= ((XLXN_312 AND XLXN_363(0)) OR (NOT XLXN_312 AND A(0))); AddrBus(1) <= ((XLXN_312 AND XLXN_363(1)) OR (NOT XLXN_312 AND A(1))); AddrBus(2) <= ((XLXN_312 AND XLXN_363(2)) OR (NOT XLXN_312 AND A(2))); AddrBus(3) <= ((XLXN_312 AND XLXN_363(3)) OR (NOT XLXN_312 AND A(3))); AddrBus(4) <= ((XLXN_312 AND XLXN_363(4)) OR (NOT XLXN_312 AND A(4))); AddrBus(5) <= ((XLXN_312 AND XLXN_363(5)) OR (NOT XLXN_312 AND A(5))); AddrBus(6) <= ((XLXN_312 AND XLXN_363(6).LFBK) OR (NOT XLXN_312 AND A(6))); AddrBus(7) <= ((XLXN_312 AND XLXN_363(7)) OR (NOT XLXN_312 AND A(7))); AddrBus(8) <= ((XLXN_312 AND XLXN_363(8)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(1))); AddrBus(9) <= ((XLXN_312 AND XLXN_363(9)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(2))); AddrBus(10) <= ((XLXN_312 AND XLXN_363(10)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(3))); AddrBus(11) <= ((XLXN_312 AND XLXN_363(11)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(4))); AddrBus(12) <= ((XLXN_312 AND XLXN_363(12)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(5))); AddrBus(13) <= ((XLXN_312 AND XLXN_363(13)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(6))); AddrBus(14) <= ((XLXN_312 AND XLXN_363(14).LFBK) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(7).LFBK)); AddrBus(15) <= ((XLXN_312 AND XLXN_363(15)) OR (NOT XLXN_312 AND XLXI_112/XLXI_127/XLXN_19(8))); ExMemData_I(0) <= DATA(0); ExMemData(0) <= ExMemData_I(0) when ExMemData_OE(0) = '1' else 'Z'; ExMemData_OE(0) <= NOT WR_INV.PIN; ExMemData_I(1) <= DATA(1); ExMemData(1) <= ExMemData_I(1) when ExMemData_OE(1) = '1' else 'Z'; ExMemData_OE(1) <= NOT WR_INV.PIN; ExMemData_I(2) <= DATA(2); ExMemData(2) <= ExMemData_I(2) when ExMemData_OE(2) = '1' else 'Z'; ExMemData_OE(2) <= NOT WR_INV.PIN; ExMemData_I(3) <= DATA(3); ExMemData(3) <= ExMemData_I(3) when ExMemData_OE(3) = '1' else 'Z'; ExMemData_OE(3) <= NOT WR_INV.PIN; ExMemData_I(4) <= DATA(4); ExMemData(4) <= ExMemData_I(4) when ExMemData_OE(4) = '1' else 'Z'; ExMemData_OE(4) <= NOT WR_INV.PIN; ExMemData_I(5) <= DATA(5); ExMemData(5) <= ExMemData_I(5) when ExMemData_OE(5) = '1' else 'Z'; ExMemData_OE(5) <= NOT WR_INV.PIN; ExMemData_I(6) <= DATA(6); ExMemData(6) <= ExMemData_I(6) when ExMemData_OE(6) = '1' else 'Z'; ExMemData_OE(6) <= NOT WR_INV.PIN; ExMemData_I(7) <= DATA(7); ExMemData(7) <= ExMemData_I(7) when ExMemData_OE(7) = '1' else 'Z'; ExMemData_OE(7) <= NOT WR_INV.PIN; HSync <= (XLXI_112/XLXI_127/XLXN_19(4) AND XLXI_112/XLXI_127/XLXN_19(1) AND XLXI_112/XLXI_127/XLXN_19(5) AND XLXI_112/XLXI_127/XLXN_19(2) AND XLXI_112/XLXI_127/XLXN_19(6) AND XLXI_112/XLXI_127/XLXN_19(3) AND XLXI_112/XLXI_127/XLXN_19(7).LFBK AND XLXI_112/XLXI_127/XLXN_19(8).LFBK); RD_INV <= XLXN_312; FDCPE_RGB_O0: FDCPE port map (RGB_O_I(0),ExMemData(0).PIN,RGB_O_C(0),'0','0'); RGB_O_C(0) <= (XLXN_311 AND NOT XLXN_312); RGB_O(0) <= RGB_O_I(0) when RGB_O_OE(0) = '1' else 'Z'; RGB_O_OE(0) <= NOT XLXN_214/XLXN_214_D2__$INT.LFBK; FDCPE_RGB_O1: FDCPE port map (RGB_O_I(1),ExMemData(1).PIN,RGB_O_C(1),'0','0'); RGB_O_C(1) <= (XLXN_311 AND NOT XLXN_312); RGB_O(1) <= RGB_O_I(1) when RGB_O_OE(1) = '1' else 'Z'; RGB_O_OE(1) <= NOT XLXN_214/XLXN_214_D2__$INT.LFBK; FDCPE_RGB_O2: FDCPE port map (RGB_O_I(2),ExMemData(2).PIN,RGB_O_C(2),'0','0'); RGB_O_C(2) <= (XLXN_311 AND NOT XLXN_312); RGB_O(2) <= RGB_O_I(2) when RGB_O_OE(2) = '1' else 'Z'; RGB_O_OE(2) <= NOT XLXN_214/XLXN_214_D2__$INT.LFBK; FDCPE_RGB_O3: FDCPE port map (RGB_O_I(3),ExMemData(3).PIN,RGB_O_C(3),'0','0'); RGB_O_C(3) <= (XLXN_311 AND NOT XLXN_312); RGB_O(3) <= RGB_O_I(3) when RGB_O_OE(3) = '1' else 'Z'; RGB_O_OE(3) <= NOT XLXN_214/XLXN_214_D2__$INT.LFBK; FDCPE_RGB_O4: FDCPE port map (RGB_O_I(4),ExMemData(4).PIN,RGB_O_C(4),'0','0'); RGB_O_C(4) <= (XLXN_311.LFBK AND NOT XLXN_312.LFBK); RGB_O(4) <= RGB_O_I(4) when RGB_O_OE(4) = '1' else 'Z'; RGB_O_OE(4) <= NOT XLXN_214/XLXN_214_D2__$INT; FDCPE_RGB_O5: FDCPE port map (RGB_O_I(5),ExMemData(5).PIN,RGB_O_C(5),'0','0'); RGB_O_C(5) <= (XLXN_311.LFBK AND NOT XLXN_312.LFBK); RGB_O(5) <= RGB_O_I(5) when RGB_O_OE(5) = '1' else 'Z'; RGB_O_OE(5) <= NOT XLXN_214/XLXN_214_D2__$INT; VSync <= (A(4) AND A(5) AND A(6) AND A(3) AND A(7)); FDCPE_WR_INV: FDCPE port map (WR_INV,WR_INV_D,WR_INV_C,'0',WR_INV_PRE); WR_INV_D <= (WR AND A1 AND NOT A0); WR_INV_C <= (NOT XLXN_311 AND XLXN_312); WR_INV_PRE <= (XLXN_311 AND XLXN_312); FTCPE_XLXI_112/XLXI_127/XLXI_1/Q0: FTCPE port map (XLXI_112/XLXI_127/XLXI_1/Q(0),'1',XLXI_112/XLXI_127/XLXI_1/Q_C(0),'0','0'); XLXI_112/XLXI_127/XLXI_1/Q_C(0) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_191: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(1),XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK,XLXI_112/XLXI_127/XLXN_19_C(1),'0','0'); XLXI_112/XLXI_127/XLXN_19_C(1) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_192: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(2),XLXI_112/XLXI_127/XLXN_19_T(2),XLXI_112/XLXI_127/XLXN_19_C(2),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(2) <= (XLXI_112/XLXI_127/XLXN_19(1).LFBK AND XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK); XLXI_112/XLXI_127/XLXN_19_C(2) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_193: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(3),XLXI_112/XLXI_127/XLXN_19_T(3),XLXI_112/XLXI_127/XLXN_19_C(3),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(3) <= (XLXI_112/XLXI_127/XLXN_19(1).LFBK AND XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK AND XLXI_112/XLXI_127/XLXN_19(2).LFBK); XLXI_112/XLXI_127/XLXN_19_C(3) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_194: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(4),XLXI_112/XLXI_127/XLXN_19_T(4),XLXI_112/XLXI_127/XLXN_19_C(4),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(4) <= (XLXI_112/XLXI_127/XLXN_19(1).LFBK AND XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK AND XLXI_112/XLXI_127/XLXN_19(2).LFBK AND XLXI_112/XLXI_127/XLXN_19(3).LFBK); XLXI_112/XLXI_127/XLXN_19_C(4) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_195: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(5),XLXI_112/XLXI_127/XLXN_19_T(5),XLXI_112/XLXI_127/XLXN_19_C(5),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(5) <= (XLXI_112/XLXI_127/XLXN_19(1).LFBK AND XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK AND XLXI_112/XLXI_127/XLXN_19(2).LFBK AND XLXI_112/XLXI_127/XLXN_19(3).LFBK AND XLXI_112/XLXI_127/XLXN_19(4).LFBK); XLXI_112/XLXI_127/XLXN_19_C(5) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_196: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(6),XLXI_112/XLXI_127/XLXN_19_T(6),XLXI_112/XLXI_127/XLXN_19_C(6),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(6) <= (XLXI_112/XLXI_127/XLXN_19(1).LFBK AND XLXI_112/XLXI_127/XLXI_1/Q(0).LFBK AND XLXI_112/XLXI_127/XLXN_19(2).LFBK AND XLXI_112/XLXI_127/XLXN_19(3).LFBK AND XLXI_112/XLXI_127/XLXN_19(4).LFBK AND XLXI_112/XLXI_127/XLXN_19(5).LFBK); XLXI_112/XLXI_127/XLXN_19_C(6) <= (A(4).LFBK AND A(5).LFBK AND A(6).LFBK AND A(3).LFBK AND A(7).LFBK); FTCPE_XLXI_112/XLXI_127/XLXN_197: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(7),XLXI_112/XLXI_127/XLXN_19_T(7),XLXI_112/XLXI_127/XLXN_19_C(7),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(7) <= (XLXI_112/XLXI_127/XLXN_19(4) AND XLXI_112/XLXI_127/XLXN_19(1) AND XLXI_112/XLXI_127/XLXN_19(5) AND XLXI_112/XLXI_127/XLXI_1/Q(0) AND XLXI_112/XLXI_127/XLXN_19(2) AND XLXI_112/XLXI_127/XLXN_19(6) AND XLXI_112/XLXI_127/XLXN_19(3)); XLXI_112/XLXI_127/XLXN_19_C(7) <= (A(4) AND A(5) AND A(6) AND A(3) AND A(7)); FTCPE_XLXI_112/XLXI_127/XLXN_198: FTCPE port map (XLXI_112/XLXI_127/XLXN_19(8),XLXI_112/XLXI_127/XLXN_19_T(8),XLXI_112/XLXI_127/XLXN_19_C(8),'0','0'); XLXI_112/XLXI_127/XLXN_19_T(8) <= (XLXI_112/XLXI_127/XLXN_19(4) AND XLXI_112/XLXI_127/XLXN_19(1) AND XLXI_112/XLXI_127/XLXN_19(5) AND XLXI_112/XLXI_127/XLXI_1/Q(0) AND XLXI_112/XLXI_127/XLXN_19(2) AND XLXI_112/XLXI_127/XLXN_19(6) AND XLXI_112/XLXI_127/XLXN_19(3) AND XLXI_112/XLXI_127/XLXN_19(7).LFBK); XLXI_112/XLXI_127/XLXN_19_C(8) <= (A(4) AND A(5) AND A(6) AND A(3) AND A(7)); XLXN_214/XLXN_214_D2__$INT <= ((NOT A(5) AND NOT A(6) AND NOT A(7)) OR (A(4) AND A(5) AND A(6) AND A(3) AND A(7)) OR (XLXI_112/XLXI_127/XLXN_19(4) AND XLXI_112/XLXI_127/XLXN_19(1) AND XLXI_112/XLXI_127/XLXN_19(5) AND XLXI_112/XLXI_127/XLXN_19(2) AND XLXI_112/XLXI_127/XLXN_19(6) AND XLXI_112/XLXI_127/XLXN_19(3) AND XLXI_112/XLXI_127/XLXN_19(7).LFBK AND XLXI_112/XLXI_127/XLXN_19(8).LFBK)); FTCPE_XLXN_311: FTCPE port map (XLXN_311,'1',CLK_I,XLXN_330.LFBK,'0'); FTCPE_XLXN_312: FTCPE port map (XLXN_312,XLXN_311.LFBK,CLK_I,XLXN_330.LFBK,'0'); FTCPE_XLXN_330: FTCPE port map (XLXN_330,XLXN_330_T,CLK_I,XLXN_330.LFBK,'0'); XLXN_330_T <= (XLXN_311.LFBK AND XLXN_312.LFBK); FDCPE_XLXN_3630: FDCPE port map (XLXN_363(0),DATA(0),XLXN_363_C(0),'0','0'); XLXN_363_C(0) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3631: FDCPE port map (XLXN_363(1),DATA(1),XLXN_363_C(1),'0','0'); XLXN_363_C(1) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3632: FDCPE port map (XLXN_363(2),DATA(2),XLXN_363_C(2),'0','0'); XLXN_363_C(2) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3633: FDCPE port map (XLXN_363(3),DATA(3),XLXN_363_C(3),'0','0'); XLXN_363_C(3) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3634: FDCPE port map (XLXN_363(4),DATA(4),XLXN_363_C(4),'0','0'); XLXN_363_C(4) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3635: FDCPE port map (XLXN_363(5),DATA(5),XLXN_363_C(5),'0','0'); XLXN_363_C(5) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3636: FDCPE port map (XLXN_363(6),DATA(6),XLXN_363_C(6),'0','0'); XLXN_363_C(6) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3637: FDCPE port map (XLXN_363(7),DATA(7),XLXN_363_C(7),'0','0'); XLXN_363_C(7) <= (WR AND NOT A1 AND NOT A0); FDCPE_XLXN_3638: FDCPE port map (XLXN_363(8),DATA(0),XLXN_363_C(8),'0','0'); XLXN_363_C(8) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_3639: FDCPE port map (XLXN_363(9),DATA(1),XLXN_363_C(9),'0','0'); XLXN_363_C(9) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36310: FDCPE port map (XLXN_363(10),DATA(2),XLXN_363_C(10),'0','0'); XLXN_363_C(10) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36311: FDCPE port map (XLXN_363(11),DATA(3),XLXN_363_C(11),'0','0'); XLXN_363_C(11) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36312: FDCPE port map (XLXN_363(12),DATA(4),XLXN_363_C(12),'0','0'); XLXN_363_C(12) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36313: FDCPE port map (XLXN_363(13),DATA(5),XLXN_363_C(13),'0','0'); XLXN_363_C(13) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36314: FDCPE port map (XLXN_363(14),DATA(6),XLXN_363_C(14),'0','0'); XLXN_363_C(14) <= (WR AND NOT A1 AND A0); FDCPE_XLXN_36315: FDCPE port map (XLXN_363(15),DATA(7),XLXN_363_C(15),'0','0'); XLXN_363_C(15) <= (WR AND NOT A1 AND A0); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572-15-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC9572-15-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 RGB_O<4> 43 ExMemData<3> 2 RGB_O<5> 44 ExMemData<2> 3 TIE 45 ExMemData<4> 4 TIE 46 ExMemData<1> 5 TIE 47 ExMemData<5> 6 TIE 48 ExMemData<0> 7 TIE 49 GND 8 GND 50 ExMemData<6> 9 CLK_I 51 AddrBus<0> 10 TIE 52 ExMemData<7> 11 DATA<0> 53 AddrBus<1> 12 TIE 54 AddrBus<15> 13 DATA<1> 55 AddrBus<2> 14 DATA<2> 56 AddrBus<10> 15 DATA<3> 57 AddrBus<3> 16 GND 58 RD_INV 17 DATA<5> 59 TDO 18 DATA<4> 60 GND 19 DATA<7> 61 AddrBus<4> 20 DATA<6> 62 AddrBus<11> 21 A1 63 AddrBus<5> 22 VCC 64 VCC 23 A0 65 AddrBus<9> 24 TIE 66 AddrBus<6> 25 WR 67 AddrBus<8> 26 TIE 68 AddrBus<7> 27 GND 69 AddrBus<13> 28 TDI 70 AddrBus<12> 29 TMS 71 WR_INV 30 TCK 72 AddrBus<14> 31 TIE 73 VCC 32 TIE 74 TIE 33 TIE 75 TIE 34 TIE 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 TIE 79 VSync 38 VCC 80 HSync 39 TIE 81 RGB_O<0> 40 TIE 82 RGB_O<1> 41 Addr15_INV 83 RGB_O<2> 42 GND 84 RGB_O<3> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572-15-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25